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March 28, 2023

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"It is important to note that instead of a single clock driving the system, in the case of a phase-locked loop, a number of clocks are synthesized and utilized. For each such clock that is synthesized, a different feedback divider is used. These divider outputs are essentially the clock signal that is expanded to the divider modulation (or divisor). The remainder of the difference in the frequency and/or phase at the loop divider output is fed back to the phase detector that is at the primary input of the loop. So, the loop involves a phase detector, a loop filter and a PLL divider. It is the combination of the loop dynamics and the PLL divider that determines the gain or frequency of the loop response. In the case of a single clock driving the system, the system dynamics directly determine the gain or frequency response and are usually modeled with a stabalizing filter (typically a low-pass filter). So, the loop dynamics alone cannot explain the behavior seen at the output of a loop when using a separate clock for PLL frequency synthesis, but PLL theory is all that is needed to explain it."2

"In a PLL, the product of the loop transfer function and the PLL divider function determines the loop gain and bandwidth. The loop response is typically measured, modeled and balanced against the frequency error detected by the loop. Difficulties may arise if the loop dynamics are not modeled correctly for example, if the loop filter contains reactive elements or if the loop function is not measured accurately. In control systems, several techniques have been developed to achieve the necessary precision, but they include analog filters, different methods of sampling the loop function and the use of digital computing."2

"First, we need to realize that the PLL primary frequency reference is not a clock generator but some kind of a signal (e.g., a voltage-controlled oscillator or a voltage-controlled crystal oscillator). If we have a sampled version of the PLL function that has a slight error, we can use it to control a frequency generator that produces the final stable oscillator frequency. In this case, the accuracy of the transfer function and the PLL divider function determines the final accuracy of the PLL system. d2c66b5586

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